1. Technical Field
The present invention is in the field of semiconductor processing and devices, more specifically in the field of non-volatile charge-trapping memory devices. In particular, the present invention relates to a method for determining programming/erase conditions and a method for operating a non-volatile charge-trapping memory device.
2. Background Art
Non-volatile memories (NVM) are characterized by the fact that once a bit is stored in a memory cell this bit will be retained even when the memory cell is no longer powered. When electrical fields are used for erasing and programming of the memory cell, the NVM devices are also known as EEPROM (Electrically-Erasable-and-Programmable-Read-Only-Memory) devices. Whereas in floating gate EEPROM devices charge is stored in a conductive layer being part of a double-capacitor structure, in charge-trapping EEPROM devices charge is stored in a non-conductive layer being part of a single-capacitor structure. In such non-conductive charge-storage layer, e.g. nitride, oxide containing polysilicon nanocrystals or metal nanoparticles, the charge will not spread out uniformly over the whole of the charge-storage layer but will be confined substantially to the location where the charge was introduced into this non-conductive charge-storage layer. Charge-trapping memory devices are characterized by the presence of discrete charge traps as memory elements contrary to floating gate memory devices where a conductive layer is used as one continuous charge trap for storing charge. Developments in EEPROM devices are increasingly focused on localized charge trapping because it eases integration and reduces stress-induced-leakage. In particular NROM™ devices using nitride as non-conductive charge-storage layer as disclosed for example by B. Eitan in international application W099/070000, are very attractive since they allow storage of two physical bits per memory cell, each bit at a different location in the nitride charge-storage layer. By injecting carriers, e.g. electrons, in the nitride layer the NROM™ cell is programmed. In order to erase the NROM™ cell opposite-type carriers are injected in the nitride layer as to compensate the charge stored during programming, e.g. holes are injected in the nitride layer to compensate the electrons already present. However, poor endurance and poor retention after cycling, i.e. repetitive programming and erasing of a cell, are major drawbacks of NROM™.
Hence there is a need to improve the endurance and charge retention characteristics of non-volatile charge-trapping memory devices, in particular of NROM™-type devices.